A novel computational fluid dynamics analysis method of predicting semiconductor junction temperatures precisely without modeling printed circuit board (PCB) line patterns was developed. First, PCBs are divided into multiple regions. The effective anisotropic thermal conductivity of each region is then assigned as follows. All the regions are divided into smaller subregions whose size is below the pattern width. The thermal conductivity of each subregion is defined by the property of the material at the center of the subregion. Next, a thermal circuit network composed of all the subregions is generated, and finally the anisotropic thermal conductivities of each region are computed by solving this thermal network matrix. When boards are divided into multiple regions, there is a convergence region size under which the analytical results show no further change. In this paper, the relationship between the size of the divided regions and the accuracy of the analytical results was investigated. It was confirmed that the calculated semiconductor junction temperatures were precisely coincident with the experimental results when the size of the regions was less than 20 times the line pattern width.
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June 2009
Research Papers
High-Accuracy Thermal Analysis Methodology for Semiconductor Junction Temperatures by Considering Line Patterns of Three-Dimensional Modules
Yutaka Kumano,
Yutaka Kumano
Printed Electronics and EMC Technology Development Office,
e-mail: kumano.yutaka@jp.panasonic.com
Panasonic Corporation
, 1006 Kadoma, Kadoma City, Osaka 571-8501, Japan
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Tetsuyoshi Ogura,
Tetsuyoshi Ogura
Printed Electronics and EMC Technology Development Office,
Panasonic Corporation
, 1006 Kadoma, Kadoma City, Osaka 571-8501, Japan
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Toru Yamada
Toru Yamada
Printed Electronics and EMC Technology Development Office,
Panasonic Corporation
, 1006 Kadoma, Kadoma City, Osaka 571-8501, Japan
Search for other works by this author on:
Yutaka Kumano
Printed Electronics and EMC Technology Development Office,
Panasonic Corporation
, 1006 Kadoma, Kadoma City, Osaka 571-8501, Japane-mail: kumano.yutaka@jp.panasonic.com
Tetsuyoshi Ogura
Printed Electronics and EMC Technology Development Office,
Panasonic Corporation
, 1006 Kadoma, Kadoma City, Osaka 571-8501, Japan
Toru Yamada
Printed Electronics and EMC Technology Development Office,
Panasonic Corporation
, 1006 Kadoma, Kadoma City, Osaka 571-8501, JapanJ. Electron. Packag. Jun 2009, 131(2): 021007 (6 pages)
Published Online: April 2, 2009
Article history
Received:
April 22, 2008
Revised:
December 11, 2008
Published:
April 2, 2009
Citation
Kumano, Y., Ogura, T., and Yamada, T. (April 2, 2009). "High-Accuracy Thermal Analysis Methodology for Semiconductor Junction Temperatures by Considering Line Patterns of Three-Dimensional Modules." ASME. J. Electron. Packag. June 2009; 131(2): 021007. https://doi.org/10.1115/1.3103947
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