Demand for off-chip bandwidth has continued to increase. It is projected by the Semiconductor Industry Association in their International Technology Roadmap for Semiconductors that by the year 2015, the chip-to-substrate area-array input-output interconnects will require a pitch of 80 μm. Compliant off-chip interconnects show great potential to address these needs. G-Helix is a lithography-based electroplated compliant interconnect that can be fabricated at the wafer level. G-Helix interconnects exhibit excellent compliance in all three orthogonal directions, and can accommodate the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate without requiring an underfill. Also, these compliant interconnects are less likely to crack or delaminate the low-$k$ dielectric material in current and future integrated circuits. The interconnects are potentially cost effective because they can be fabricated in batch at the wafer level and using conventional wafer fabrication infrastructure. In this paper, we present an integrative approach, which uses interconnects with varying compliance and thus varying electrical performance from the center to the edge of the die. Using such a varying geometry from the center to the edge of the die, the system performance can be tailored by balancing electrical requirements against thermomechanical reliability concerns. The test vehicle design to assess the reliability and electrical performance of the interconnects is also presented. Preliminary fabrication results for the integrative approach are presented and show the viability of the fabrication procedure. The results from reliability experiments of helix interconnects assembled on an organic substrate are also presented. Initial results from the thermal cycling experiments are promising. Results from mechanical characterization experiments are also presented and show that the out-of-plane compliance exceeds target values recommended by industry experts. Finally, through finite element analysis simulations, it is demonstrated that the die stresses induced by the compliant interconnects are an order of magnitude lower than the die stresses in flip chip on board (FCOB) assemblies, and hence the compliant interconnects are not likely to crack or delaminate low-$k$ dielectric material.

1.
Ho
,
R.
,
Mai
,
K. W.
, and
Horowitz
,
M. A.
, 2004, “
The Future of Wires
,”
Proc. IEEE
0018-9219,
89
, pp.
490
504
.
2.
Hofstee
,
H. P.
, 2004, “
Future Microprocessors and Off-Chip SOP Interconnect
,”
1521-3323,
27
, pp.
301
313
.
3.
http://public.itrs.nethttp://public.itrs.net, International Technology Roadmap for Semiconductors, 2005.
4.
Kacker
,
K.
,
Lo
,
G.
, and
Sitaraman
,
S. K.
, 2005, “
Assembly and Reliability Assessment of Lithography-Based Wafer-Level Compliant Chip-To-Substrate Interconnects
,”
2005 Proceedings of the 55th Electronic Components and Technology
, Pt. 1, pp.
545
550
.
5.
Zhu
,
Q.
,
Ma
,
L.
, and
Sitaraman
,
S. K.
, 2004, “
Development of G-Helix Structure as Off-Chip Interconnect
,”
ASME J. Electron. Packag.
1043-7398,
126
, pp.
237
246
.
6.
Braunisch
,
H.
,
Hwang
,
K.
, and
Emery
,
R. D.
, 2004, “
Compliant Die-Package Interconnects at High Frequencies
,”
Proceedings of the 54th Electronic Components and Technology Conference
,
Las Vegas, NV
, pp.
1237
1243
.
7.
Classe
,
F. C.
, and
Sitaraman
,
S. K.
, 2003, “
Asymmetric Accelerated Thermal Cycles: An Alternative Approach to Accelerated Reliability Assessment of Microelectronic Packages
,”
Proceedings of the Fifth Electronics Packaging Technology Conference
.
8.
Yeo
,
A.
,
Lee
,
C.
, and
Pang
,
J. H. L.
, 2006, “
Flip Chip Solder Joint Reliability Analysis Using Viscoplastic and Elastic-Plastic-Creep Constitutive Models
,”
IEEE Trans. Compon. Packag. Technol.
1521-3331,
29
(
2
), pp.
355
363
.
9.
Gustafsson
,
G.
,
Guven
,
I.
,
,
V.
, and
,
E.
, 2000, “
Finite Element Modeling of BGA Packages for Life Prediction
,”
2000 Proceedings of the 50th Electronic Components and Technology Conference
, pp.
1059
1063
.
10.
Iannuzzelli
,
R.
, 1991, “
Predicting Plated-Through-Hole Reliability in High-Temperature Manufacturing Process
,”
Proceedings of the 41st Electronic Components and Technology Conference
, pp.
410
421
.
11.
Wang
,
G. Z.
,
Cheng
,
Z. N.
,
Becker
,
K.
, and
Wilde
,
J.
, 2001, “
Applying Anand Model to Represent the Viscoplastic Deformation Behavior of Solder Alloys
,”
ASME J. Electron. Packag.
1043-7398,
123
, pp.
247
253
.
12.
Engelmaier
,
W.
, 1982, “
Results of the IPC Copper Foil Ductility Round-Robin Study
,”
IPC Publication No. 947
.
13.
Prabhu
,
A. S.
,
Barker
,
D. B.
, and
Pecht
,
M. G.
, 1995, “
A Thermo-Mechanical Fatigue Analysis of High Density Interconnect Vias
,”
,
10
(
1
), pp.
187
216
.
14.
Intel Corporation
, 2001, “
Mechanical and Electrical Considerations of Compliant Interconnect
,” Internal Project Report.
15.
JEDEC Solid State Technology Association
, 2000, Thermal Cycling Standard No. JESD22-A104-B.