The nested finite element methodology (NFEM) presented in Part I of this series, is used in this paper to analyze the viscoplastic stress-state in a flip-chip-on-board (FCOB) and a chip scale package subjected to temperature cycling loads. The results are validated with conventional finite element method (CFEM). An energy-partitioning (EP) damage model is used to predict cycles to failure, based on the energy densities obtained from NFEM and CFEM, and results are compared with experiments.
1.
IPC SM 785, 1992, “guidelines for accelerated testing of surface mount solder attachments,” Proposed Standard of IPC Surface Mount Task Group, Institute for Interconnecting Packing Electronic Circuits, Lincolnwood, IL.
2.
Engelmaier, W., 1982, “Fatigue life of leadless chip carrier solder joints during power cycling,” Proceedings of the Technical Program of the 2nd Annual International Electronics Packaging Society Conference, San Diego, CA, Nov. 15–17, 1982.
3.
Yeh
, C.
, Zhou
, W.
, and Wyatt
, K.
, 1996
, “Parametric finite element analysis of flip chip reliability
,” Microcircuits and Electronic Packaging
,19
, No. 2
, pp. 120
–127
.4.
Lau, J. H., and Pao, Y, 1997, Solder joint reliability of BGA, CSP and fine pitch SMT assemblies, McGraw-Hill, NY.
5.
Doi
, K.
, Hirano
, N.
, Okada
, T.
, Hiruta
, Y.
, Sudo
, T.
, and Mukai
, M.
, 1996
, “Prediction of thermal fatigue for encapsulated flip chip interconnection
,” Microcircuits and Electronic Packaging
,19
, No. 3
, pp. 231
–237
.6.
Schubert, A., Dudek, R., Auersperg, J., Vogel, D., Michel, B., and Reichl, H., 1997, “Thermo-Mechanical reliability analysis of flip chip assemblies by combined microDAC and the finite element method” INTERpack ’97, EEP-Vol. 19-1, pp. 1647–1654.
7.
Le Gall, C. A., Qu, J., and McDowell, D. L., 1997, “Influence of die size on the magnitude of thermomechanical stresses in flip chips directly attached to printed wiring board,” InterPACK’97, EEP-Vol. 19-2, pp. 1663–1670.
8.
Okura, J. H., Darbha, K., Shetty, S., Dasgupta, A., and Caers, J., 1999, “Underfill design guidelines for flip chip on board assemblies,” ECTC Conference, San Diego, CA.
9.
Dasgupta, A., Oyan, C., Booker, D., and Pecht, M., 1992, “Solder Creep-Fatigue Analysis by an Energy-Partitioning Approach,” Trans. ASME JEP, Vol. 114, pp. 152–160.
10.
Darbha, K., and Dasgupta, A., 1999, “A Nested Finite Element Methodology for stress analysis of flip chip on board Assemblies-Part 1: Elastic Analysis,” ASME Interpack ’99, June, Maui, Hawaii.
11.
Okura, J. H., Darbha, K., and Dasgupta, A., 1998, “Effect of underfill in flip chip on board assemblies,” 10th Symposium on Surface Mount Assemblies, ASME Winter Annual Conference, Anaheim, CA.
12.
Darbha
, K.
, Okura
, J. H.
, Shetty
, S.
, Dasgupta
, A.
, Reinikainen
, T.
, Zhu
, J.
, and Caers
, J.
, 1999
, “Thermomechanical Durability Analysis of Flip Chip Solder Interconnects: Part 2-with underfill
,” ASME J. Electron. Packag.
, 121
, No. 4
, pp. 237
–241
.13.
Baggerman
, A. F. J.
, Caers
, J. F. J. M.
, Wondergem
, J. J.
, and Wagemans
, A. G.
, 1996
, “Low-cost flip chip on board
,” IEEE Transactions on Components, Packgaing, and Manufacturing Technology-Part B
, 19
, No. 4
, pp. 736
–746
.14.
Lau, J., and Ricky-Lee, S. W., 1999, Chip Scale Package-Design, materials, processes, reliability and application McGraw Hill, NY, Chapter 16, pp. 259–282.
15.
Banks D. R., Heim, C. G., and Lewis, R. H., 1993, “Second-Level assembly of column-grid array packages,” Proceedings of the SMI Conference, Aug. 1993, pp. 92–98.
16.
Pecht, M., 1991, Handbook of electronic packaging and design, Marcel Dekker, NY, pp. 732–734.
17.
Tribula, D., and Morris, J. W., 1989, “Creep shear of experimental solder joints,” ASME Winter Annual Meeting, 89-WA/EEP-30, San Francisco, CA.
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