A novel and reliable wafer level chip scale package (WLCSP) is investigated in this paper. It consists of a copper conductor layer and two low cost dielectric layers. The bump geometry consists of the eutectic solder, the copper core, and the under bump metallurgy. Nonlinear time-temperature-dependent finite element analyses are performed to determine the shear stress, shear creep strain, shear stress and shear creep strain hysteresis loops, and creep strain energy density of the corner solder joint. The thermal-fatigue life of the corner solder joint is then predicted by the averaged creep strain energy density range per cycle and a linear fatigue crack growth rate theory. The WLCSP solder bumps are also subjected to shear test. Finally, the WLCSP solder joints are subjected to both mechanical shear and thermal cycling tests. [S1043-7398(00)01004-5]

Issue Section:
Technical Papers
Keywords:
integrated circuit reliability, chip scale packaging, soldering, finite element analysis, shear strength, thermal stress cracking, creep
Topics:
Corners (Structural elements), Creep, Semiconductor wafers, Shear (Mechanics), Solder joints, Solders, Temperature, Finite element analysis, Reliability, Manufacturing, Fatigue
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