Abstract
One of the leading contributors to assembly and reliability issues in electronic packaging arises from warpage and interfacial stresses stemming from coefficient of thermal expansion (CTE) mismatch of the interfacing components. Trends toward miniaturizing and increasing density of the electronic packages exacerbate the assembly problems, leading to issues such as die cracking and board level assembly yield loss. One potential solution may be found in the inclusion of auxetic structures, which demonstrate negative Poisson’s ratio through re-entrant geometries, which has been investigated for use in augmented structural mechanics for impact energy absorption. Because of the unique structural design, auxetics become thicker perpendicularly under an applied tensile load, unlike typical material loading responses. This interesting behavior has opportunity for integration into electronic packages for stress mitigation under thermal cycling since the structures can disrupt the typical expansion behavior. Here, auxetic trace geometries and structures were evaluated in various packaging implementations (die and substrate level) for warpage and stress reduction under thermal cycling conditions. By replacing standard Manhattan-style layouts and power and ground plane features with re-entrant trace geometries, reductions in thermomechanically induced interfacial stresses were observed, in addition to considering heat spreading properties within a package. Herein, deformation of silicon chip with addition of raised re-entrant Evans auxetics and raised ellipse shape auxetic traces as well as deformation of direct bonded copper (DBC) substrate with and without re-entrant auxetic patterned pads are estimated and compared using Finite Element Analysis (FEA) in ANSYS software. To demonstrate the benefits of passive auxetic traces, a planar transformer with re-entrant Evans auxetic patterns on PCB layers has been examined under full-load operating condition and compared with a traditionally patterned transformers. A better thermal distribution and lower maximum temperature in the device are achieved by including auxetic patterned features. FEA simulation results also show stress reduction in windings and lower deformation in PCB layers. Inclusion of auxetic structures in passive metal deposition layers which are not part of the circuit is shown to reduce maximum stress and warp deflection, as well as improve thermal gradient distribution and reduce overall temperature for 2D planar and 3D stacked packages. Consequently, use of auxetic features may extend package reliability significantly.
