For the next generation of high performance computers, the new challenges are to shorten the distance for transporting data (to accelerate the transfer of information) between multi-microprocessors and memories, and to cool these electronic components despite the increased heat flux that results from increased transistor density. Recent technological advances show a tendency for the development of 3D integrated circuit stacked architectures with interlayer cooling (multi-microchannels in the silicon layers). However, huge challenges exist in such design/concept, i.e. flow distribution to hundreds microchannels distributed in the different interlayers, thermo-hydrodynamic and geometrical limitations, manufacturing etc. 3D-ICs with interlayer cooling are still about a decade away, so a viable shorter term goal is 3D stacks with backside cooling, taking advantage of Si layers now able to be thineer down to only 50 μm thickness. Thus, the present work presents thermo-hydrodynamic simulations for 3D stacks considering only a backside cooler, which simplifies considerably the assembly and guarantees a high level of reliability. In summary, the results showed that this concept is thermally feasible and potentially that interlayer microchannels (between stacks) will not be necessary.
- Electronic and Photonic Packaging Division
3D Stacks of Microprocessors and Memories With Backside Two-Phase Multi-Microchannel Cooler
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Marcinichen, JB, & Thome, JR. "3D Stacks of Microprocessors and Memories With Backside Two-Phase Multi-Microchannel Cooler." Proceedings of the ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. Volume 1: Advanced Packaging; Emerging Technologies; Modeling and Simulation; Multi-Physics Based Reliability; MEMS and NEMS; Materials and Processes. Burlingame, California, USA. July 16–18, 2013. V001T04A020. ASME. https://doi.org/10.1115/IPACK2013-73263
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