Thermal transport in microelectronic devices spans length scales from tens of nanometers to hundreds of millimeters. One of the major challenges in maintaining quality and reliability in today’s microelectronic devices comes from the ever increasing level of integration in the device fabrication as well as the high level of current densities that are carried through the microchip during operation. Consequently, significant opportunities for energy efficiency exist at various levels of the length scale hierarchy by optimization of thermal management resources.

In this study, we developed a computationally efficient and accurate multi-scale reduced order transient thermal methodology consisting of hybrid implementation of two different multi-scale approaches: 1. “Progressive Zoom-in” method and 2. “Proper Orthogonal Decomposition (POD)” technique. The suggested approach provides the ability to predict different thermal scenarios based on one representative thermal scenario, while maintaining the desired spatial and temporal accuracy. In this paper, a Flip Chip Ball Grid Array (FCBGA) package was considered for hybrid modeling. To demonstrate the capability of POD method in predicting different thermal scenarios, the chip is divided into ten function blocks. Each of these blocks had a different randomly generated dynamic power source. To validate this methodology, the results were compared with a finite element (FE) model developed in COMSOL®. The behavior of the POD model was in good agreements with the corresponding FE model. This close correlation provides the capability of predicting other thermal scenarios based on a smaller sample set which can significantly decrease the computational cost.

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