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Research Papers

Synchronization of a Single-phase Photovoltaic Generator With the Low-Voltage Utility Grid

[+] Author and Article Information
Nader Anani, Omar Al-Kharji, Prasad Ponnapalli

School of Engineering, Division of Electrical and Electronic Engineering,  Manchester Metropolitan University, Manchester, M1 5GD, United Kingdom

Saleh Al-Araji, Mahmoud Al-Qutayri

College of Engineering,  Khalifa University, P. O. Box 573, Sharjah Campus, Sharjah, UAE

J. Sol. Energy Eng 134(1), 011007 (Nov 29, 2011) (8 pages) doi:10.1115/1.4005337 History: Received March 18, 2011; Revised October 08, 2011; Published November 29, 2011; Online November 29, 2011

The increased generation of electrical energy from renewable sources and its integration into the low voltage grid have necessitated regulations governing the connection of renewable energy generators to the grid. This was deemed necessary to preserve the integrity and the correct operation of the grid. This paper presents a new architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock loop (PLL) to synchronize a PV inverter with the grid. The proposed system has been tested by simulation using simulink /matlab . The test results demonstrate the ability of the system to synchronize a PV inverter with the grid and to re-establish synchronization following a sudden perturbation in the grid voltage such as a single or a multistep change in phase. The system is digital and can be readily implemented using an FPGA (field programmable gate array) and hence can be easily embedded in a home or small scale single-phase PV inverter.

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Copyright © 2012 by American Society of Mechanical Engineers
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Figures

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Figure 1

Skeleton of a standalone PV system

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Figure 2

A grid-connected inverter

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Figure 3

A block diagram of the proposed synchronization system

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Figure 4

(a) Phase step input, (b) phase error for phase step input, and (c) phase plane for phase step input

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Figure 5

(a) Consecutive phase step input, (b) phase error for consecutive phase step input, and (c) phase plane for consecutive phase step input

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Figure 6

(a) Phase error for phase step input with SNR = 20 dB, (b) phase plane for phase step input with SNR = 20 dB, and (c) phase error steady state pdf of 5% Doppler shift

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Figure 7

(a) Grid signal with 35% THD and (b) Phase error for phase step input with 35% THD

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Figure 8

(a) Grid voltage waveform with induced voltage sag, (b) phase error corresponding to the voltage sag test, and (c) phase plane corresponding to the voltage sag test

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